1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip design and fabrication, and more particularly, to changing of via density to improve wafer surface planarity.
2. Background Art
Fabrication of copper interconnects in today's integrated circuits usually involves “via first” dual damascene. Vias are first etched into a dielectric or dielectric stack, usually down to an etch stop layer. After resist strip, the line level processing is done, which first involves spin coating an underlayer material which fills the via holes, “planarizing” the surface. Subsequent layers are then deposited or spin coated, and line level lithography is then done. However, the degree to which the underlayer planarizes the wafer surface has been found to depend on the via density. As shown in FIG. 1, high via density areas “consume” more of the underlayer to fill the holes and this results in a wafer surface which, after underlayer coating, has height differences between high via density and low via density areas (other things being equal, since metal densities at prior levels also effect surface height).
The lithographic materials which are coated on top of the underlayer generally do not planarize over such large distances, and the result is that the distance from the surface of the photoresist layer to the lens of the exposure tool varies from place to place within the chip. The exposure tool reads the surface planarity prior to exposure and chooses a plane of best average focus (which is varied continuously as the exposure slit scans across the reticle field). A non-planar surface must, of course, have some areas which are in better focus than others, if a planar exposure is done across the slit surface. If, for instance, the majority of the slit area has a high density of vias, the line images over the low via density areas will be in particularly poor focus (other things being equal) and therefore will be more subject to scumming, poor critical dimension (CD) control and associated yield problems. The difference in the best focus setting conditions for imaging minimum dimension lines (45 nm technology node) over high density via areas versus low density via areas may be a significant portion of the depth of focus for today's critical lithography processes. Other effects, such as non-planarity due to chemical mechanical polish (CMP), and lithography tool control factors (lens distortions, chuck imperfections, etc.) also consume portions of the available depth of focus.